1. Field of the Invention
The present invention relates to semiconductor devices, such as, for example, SRAMs (static random access memories), and memory systems and electronic apparatuses equipped with the same.
2. Description of the Related Art
SRAMs are a type of semiconductor memory devices that do not require a refreshing operation and therefore have properties that can simplify the system and lower power consumption. For this reason, the SRAMs are widely used as memories for electronic equipment, such as mobile phones.
The present invention provides semiconductor devices that can reduce cell area. The present invention also provides memory systems and electronic apparatuses that include such semiconductor devices.
Additional features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a semiconductor device having a memory cell including a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor, the semiconductor device includes a first gatexe2x80x94gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor; a second gatexe2x80x94gate electrode layer including a gate electrode of the second load transistor and a gate electrode of the second driver transistor; a first drainxe2x80x94drain wiring layer that forms a part of a connection layer that electrically connects a drain of the first load transistor and a drain of the first driver transistor; a second drainxe2x80x94drain wiring layer that forms a part of a connection layer that electrically connects a drain of the second load transistor and a drain of the second driver transistor; a first drain-gate wiring layer that forms a part of a connection layer that electrically connects the first gatexe2x80x94gate electrode layer and the second drainxe2x80x94drain wiring layer; and a second drain-gate wiring layer that forms a part of a connection layer that electrically connects the second gatexe2x80x94gate electrode layer and the first drainxe2x80x94drain wiring layer. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located in a layer below the first drainxe2x80x94drain wiring layer, and the second drain-gate wiring layer is located in a layer above the first drainxe2x80x94drain wiring layer.
Because the first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers, the pattern density of each of the wiring layers where the first drain-gate wiring layer and the second drain-gate wiring layer are formed can be reduced, compared to the case where the first drain-gate wiring layer and the second drain-gate wiring layer are formed in the same layer. As a result, the cell area can be made smaller.
In another aspect, the present invention provides a memory system including the above semiconductor device.
In yet another aspect, the present invention provides an electronic apparatus including the above semiconductor device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.